1 data sheet acquired from harris semiconductor schs134e features hysteresis on clock inputs for improved noise immunity and increased input rise and fall times asynchronous reset complementary outputs buffered inputs typical f max = 60mhz at v cc = 5v, c l = 15pf, t a = 25 o c fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh description the ?c73 and cd74hct73 utilize silicon gate cmos technology to achieve operating speeds equivalent to lsttl parts. they exhibit the low power consumption of standard cmos integrated circuits, together with the ability to drive 10 lsttl loads. these ?p-?ps have independent j, k, reset and clock inputs and q and q outputs. they change state on the negative-going transition of the clock pulse. reset is accomplished asynchronously by a low level input. this device is functionally identical to the hc/hct107 but differs in terminal assignment and in some parametric limits. the hct logic family is functionally as well as pin compatible with the standard ls logic family. pinout cd54hc73 (cerdip) cd74hc73, cd74hct73 (pdip, soic) top view ordering information part number temp. range ( o c) package cd54hc73f3a -55 to 125 14 ld cerdip cd74hc73e -55 to 125 14 ld pdip cd74hc73m -55 to 125 14 ld soic cd74hc73mt -55 to 125 14 ld soic cd74hc73m96 -55 to 125 14 ld soic CD74HCT73E -55 to 125 14 ld pdip cd74hct73m -55 to 125 14 ld soic note: when ordering, use the entire part number. the suf? 96 denotes tape and reel. the suf? t denotes a small-quantity reel of 250. 1cp 1r 1k v cc 2cp 2r 2j 1j 1q 1q gnd 2k 2q 2q 1 2 3 4 5 6 7 14 13 12 11 10 9 8 february 1998 - revised september 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc73, cd74hc73, cd74hct73 dual j-k flip-flop with reset negative-edge trigger [ /title ( cd74 h c73, c d74 h ct73 ) / sub- j ect ( dual j -k f lip- f lop
2 functional diagram logic diagram truth table inputs outputs r cp j k q q lxxxlh h l l no change h hlhl h lhlh h h h toggle h h x x no change h =high level (steady state) l =low level (steady state) x = irrelevant = high-to-low transition 2 r 12 13 1 q 1q 6 2 1 r 2k 10 5 9 8 2 q 2q 2 cp ff 1 ff 2 gnd = 11 v cc = 4 2j 7 1k 3 1 1cp 1j 14 na j k cl cl r 12 (9) q 13 (8) q 14 (7) 3(10) j k 1 (5) cp 2 (6) r cd54hc73, cd74hc73, cd74hct73
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc drain current, per output, i o for -0.5v < v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 1) ja ( o c/w) e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 maximum junction temperature (hermetic package or die) . . . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads ---------v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads ---------v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a cd54hc73, cd74hc73, cd74hct73
4 quiescent device current i cc v cc or gnd 0 6 - - 4 - 40 - 80 a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd - 5.5 - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 4 - 40 - 80 a additional quiescent device current per input pin: 1 unit load ? i cc (note 2) v cc - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 2. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads all 0.3 note: unit load is ? i cc limit speci?d in dc electrical speci?a- tions table, e.g., 360 a max at 25 o c. hc types hct types input level v cc 3v v s 50% v cc 1.3v note: transition times and propagation delay times prerequisite for switching speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types cp pulse width t w -c l = 50pf 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns r pulse width t w -c l = 50pf 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns cd54hc73, cd74hc73, cd74hct73
5 setup time, j, k to cp t su c l = 50pf 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns hold time, j, k to cp t h c l = 50pf 2 3 - - 3 - 3 - ns 4.5 3 - - 3 - 3 - ns 63--3-3-ns removal time t rem -c l = 50pf 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns cp frequency f max c l = 50pf 2 6 - - 5 - 4 - mhz 4.5 30 - - 25 - 20 - mhz c l = 15pf 5 - 60 - ----mhz c l = 50pf 6 35 - - 29 - 23 - mhz hct types cp pulse width t w c l = 50pf 4.5 16 - - 20 - 24 - ns r pulse width t w cl = 50pf 4.5 18 - - 23 - 27 - ns setup time, j, k to cp t su cl = 50pf 4.5 16 - - 20 - 24 - ns hold time, j, k to cp t h cl = 50pf 4.5 3 - - 3 - 3 - ns removal time t rem cl = 50pf 4.5 12 - - 15 - 18 - ns cp frequency f max cl = 50pf 4.5 30 - - 25 - 20 - mhz cl = 15pf 5 - 60 - ----mhz switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay, cp to q t plh , t phl c l = 50pf 2 - - 160 - 200 - 240 ns 4.5 - - 32 - 40 - 48 ns cl = 15pf 5 - 13 - ----ns c l = 50pf 6 - - 28 - 34 - 41 ns propagation delay, cp to q t plh , t phl c l = 50pf 2 - - 160 - 200 - 240 ns 4.5 - - 32 - 40 - 48 ns c l = 15pf 5 - 13 - ----ns c l = 50pf 6 - - 28 - 34 - 41 ns propagation delay, r to q, q t plh , t phl c l = 50pf 2 - - 145 - 180 - 220 ns 4.5 - - 29 - 36 - 44 ns c l = 15pf 5 - 12 - ----ns c l = 50pf 6 - - 25 - 31 - 38 ns output transition time t tlh , t thl c l = 50pf 2 - - 75 - 95 18 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns prerequisite for switching speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max cd54hc73, cd74hc73, cd74hct73
6 input capacitance c i - - - - 10 - 10 - 10 pf power dissipation capacitance (notes 3, 4) c pd - 5-28-----pf hct types propagation delay, cp to q t plh , t phl c l = 50pf 4.5 - - 38 - 48 - 57 ns propagation delay, cp to q t plh , t phl cl = 50pf 4.5 - - 36 - 45 - 54 ns propagation delay, r to q, q t plh , t phl cl = 50pf 4.5 - - 34 - 43 - 51 ns output transition time t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c i - - - - 10 - 10 - 10 pf power dissipation capacitance (notes 3, 4) c pd - 5-28-----pf notes: 3. c pd is used to determine the dynamic power consumption, per flip-flop. 4. p d =c pd v cc 2 f i + c l v cc 2 f o where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?ations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 2. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 3. hct clock pulse rise and fall times and pulse width figure 4. hc and hcu transition times and propaga- tion delay times, combination logic figure 5. hct transition times and propagation delay times, combination logic clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = f cl i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% cd54hc73, cd74hc73, cd74hct73
7 figure 6. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits figure 7. hct setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits test circuits and waveforms (continued) t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) t r c l t f c l gnd 3v gnd 3v 1.3v 2.7v 0.3v gnd clock input data input output set, reset or preset 3v 1.3v 1.3v 1.3v 90% 10% 1.3v 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) 1.3v t h(h) 1.3v cd54hc73, cd74hc73, cd74hct73
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-8515301ca active cdip j 14 1 tbd call ti level-nc-nc-nc cd54hc73f active cdip j 14 1 tbd call ti level-nc-nc-nc cd54hc73f3a active cdip j 14 1 tbd call ti level-nc-nc-nc cd74hc73e active pdip n 14 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc73ee4 active pdip n 14 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc73m active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc73m96 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc73m96e4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc73me4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc73mt active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc73mte4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HCT73E active pdip n 14 25 pb-free (rohs) cu nipdau level-nc-nc-nc CD74HCT73Ee4 active pdip n 14 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hct73m active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct73me4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited package option addendum www.ti.com 26-sep-2005 addendum-page 1
information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 26-sep-2005 addendum-page 2
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